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參數(shù)資料
| 型號： | WM8191 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS BI-DIR 6.0V 400W SMA |
| 中文描述： | 14位6MSPS獨聯(lián)體/防治荒漠化公約模擬前端/數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 355K |
| 代理商： | WM8191 |
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WM8191
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.1 April 2001
12
TIMING CONTROL
R
S
S/H
4-BIT
RLC DAC
CL
+
+
-
TO OFFSET DAC
RLC
CDS
FROM CONTROL
INTERFACE
S/H
V
S
FROM CONTROL
INTERFACE
MCLK
VSMP
RLC/ACYC
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
CDS
C
IN
RINP
VRLC/
VBIAS
2
1
EXTERNAL VRLC
VRLCEXT
Figure 8 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected pixel-by-pixel by pin RLC/ACYC. Figure 9
illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 10).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
MCLK
VSMP
RLC/ACYC
CL
(CDSREF = 01)
INPUT VIDEO
1
X
X
0
X
X
0
RGB
RGB
No RLC on this Pixel
RLC on this Pixel
Programmable Delay
RGB
Figure 9 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 8) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
s
/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 10.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WM8192 | TVS UNIDIRECT 400W 6.5V SMA |
| WM8196 | (8+8)BIT OUTPUT 16-BIT CIS/CCD AFE/DIGITISER |
| WM8199 | 20MSPS 16-bit CCD Digitiser |
| WM8199CDR | TVS BIDIRECT 400W 60V SMA |
| WM8199CDS | TVS UNIDIRECT 400W 64V SMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WM8192 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:(8+8) Bit Output 16-bit CIS/CCD AFE/Digitiser |
| WM8195 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser |
| WM8195_05 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser |
| WM8195SCFT/RV | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 12MSPS 3C AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| WM8195SCFT/V | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 12MSPS 3Ch AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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