參數(shù)資料
型號: WJLXT972MLC.A4SE001
廠商: CORTINA SYSTEMS INC
元件分類: 網(wǎng)絡接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝: LEAD FREE, LQFP-48
文件頁數(shù): 74/94頁
文件大?。?/td> 1235K
代理商: WJLXT972MLC.A4SE001
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
76
Document Number: 302875-004
Revision Date: February 18, 2005
Figure 34. Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Table 39. Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
RESET_L pulse width
t1
10
ns
RESET_L recovery delay
2
t2
300
s–
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance. The PHY comes out of reset after a delay of no more than 300
s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300
s before accessing the MDIO port.
t2
RESET_L
MDIO, and
so on
t1
B3495-01
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