參數(shù)資料
型號(hào)： WJLXT972MLC.A4SE001
廠商： CORTINA SYSTEMS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： LEAD FREE, LQFP-48
文件頁數(shù)： 54/94頁
文件大?。?/td> 1235K
代理商： WJLXT972MLC.A4SE001
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
58
Document Number: 302875-004
Revision Date: February 18, 2005
5.10.4
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. Table 17 lists the four BSR modes of operation.
5.10.5
Device ID Register
Table 18 lists the bits for the Device ID register. For the current version of the JEDEC continuation
characters, see the specification update for the LXT972M Transceiver.
Table 17. BSR Mode of Operation
Mode
Description
1Capture
2Shift
3
Update
4
System Function
Table 18. Device ID Register for Intel
LXT972M Transceiver
Bits 31:28
Bits 27:12
Bits 11:8
Bits 7:1
Bit 0
Version
Part ID (Hex)
JEDEC Continuation Characters
JEDEC ID1
Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE
(1111 1110), which becomes 111 1110.
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