參數(shù)資料
型號： WJLXT972MLC.A4SE001
廠商： CORTINA SYSTEMS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： LEAD FREE, LQFP-48
文件頁數(shù)： 33/94頁
文件大?。?/td> 1235K
代理商： WJLXT972MLC.A4SE001
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
39
Document Number: 302875-004
Revision Date: February 18, 2005
5.6.1
MII Clocks
The LXT972M Transceiver is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
Figure 8 through Figure 10 show the clock cycles for each mode.
Note:
The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
LXT972M Transceiver samples these signals on the rising edge of TX_CLK.
Figure 8. Clocking for 10BASE-T
Figure 9. Clocking for 100BASE-X
RX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
Constant 25 MHz
XI
B3390-01
RX_CLK
2.5 MHz during auto-negotiation
TX_CLK
Constant 25 MHz
XI
25 MHz once 100BASE-X
Link Established
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
Link Established
B3391-01
相關(guān)PDF資料
PDF描述
WJLXT972MLC.A4SE000 DATACOM, ETHERNET TRANSCEIVER, PQFP48
WJLXT972MLC.A4SE001 DATACOM, ETHERNET TRANSCEIVER, PQFP48
WJLXT972MLC.A4SE000 DATACOM, ETHERNET TRANSCEIVER, PQFP48
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WJLXT972MLC.A4 DATACOM, ETHERNET TRANSCEIVER, PQFP48
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