參數(shù)資料
型號(hào): WJLXT972MLC.A4SE001
廠商: CORTINA SYSTEMS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝: LEAD FREE, LQFP-48
文件頁數(shù): 21/94頁
文件大?。?/td> 1235K
代理商: WJLXT972MLC.A4SE001
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
28
Document Number: 302875-004
Revision Date: February 18, 2005
5.2.3
Configuration Management Interface
The LXT972M Transceiver provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
5.2.3.1
MDIO Management Interface
MDIO management interface topics include the following:
The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972M Transceiver. The MDIO interface consists of a
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972M Transceiver also supports additional registers for expanded functionality. The
LXT972M Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31) and Y is
the bit number (0-15).
5.2.3.1.1
MDIO Addressing for Intel LXT972M Transceiver
The MDIO addressing protocol allows a controller to communicate with multiple LXT972M
Transceivers.As listed in Table 12, pins ADDR[1:0] determine the PHY device address that is
selected.
Table 12. Intel LXT972M Transceiver - PHY Device Address Selections
ADDR1
(Pin 11)
ADDR0
(Pin 10)
PHY Device
Address
Selected
00
0
01
1
10
28
11
29
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