參數(shù)資料
型號(hào)： WJLXT972MLC.A4SE000
廠商： CORTINA SYSTEMS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： LEAD FREE, LQFP-48
文件頁數(shù)： 65/94頁
文件大?。?/td> 1235K
代理商： WJLXT972MLC.A4SE000
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
68
Document Number: 302875-004
Revision Date: February 18, 2005
Figure 24 does not show the TX_ER signal.
.
Figure 24. Intel LXT972M Transceiver 100BASE-TX Transmit Timing
t1
t2
t5
t3
t4
0ns
250ns
TXCLK
TX_EN
TXD[3:0]
TPO
CRS
B3454-03
Note: Timing diagram depicts 4B mode.
Table 31. Intel LXT972M Transceiver 100BASE-TX Transmit Timing Parameters
Parameter
Symbol
Min
Typ
1
Max
Units2
Test Conditions
TXD[3:0], TX_EN setup to TX_CLK
High
t1
12
–
ns
–
TXD[3:0], TX_EN hold from TX_CLK
High
t2
0
–
ns
–
TX_EN sampled to CRS asserted
t3
20
–
24
BT
–
TX_EN sampled to CRS de-asserted
t4
24
–
28
BT
–
TX_EN sampled to TPO out (Tx
latency)
t5
5.3
–
5.7
BT
–
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
testing.
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
rate. 100BASE-T bit time = 10-8 s or 10 ns.
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