參數(shù)資料
型號: WJLXT972MLC.A4SE000
廠商: CORTINA SYSTEMS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝: LEAD FREE, LQFP-48
文件頁數(shù): 20/94頁
文件大小: 1235K
代理商: WJLXT972MLC.A4SE000
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
27
Document Number: 302875-004
Revision Date: February 18, 2005
5.2.2
MII Data Interface
The LXT972M Transceiver supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes data
between the LXT972M Transceiver and a Media Access Controller (MAC). Separate parallel buses
are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The
speed is set automatically, once the operating conditions of the network link have been determined.
Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength may
be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive
loads, through multiple vias, or through a connector. The MII drive strength in the LXT972M
Transceiver can be increased by setting Register bit 26.11 through software control. Setting
Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV,
RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
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