參數(shù)資料
型號(hào)： WJLXT972MLC.A4SE000
廠商： CORTINA SYSTEMS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： LEAD FREE, LQFP-48
文件頁數(shù)： 32/94頁
文件大?。?/td> 1235K
代理商： WJLXT972MLC.A4SE000
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
38
Document Number: 302875-004
Revision Date: February 18, 2005
5.6
MII Operation
This section includes the following topics:
The LXT972M Transceiver implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT972M Transceiver (TXD), and for passing data received from the line (RXD) to the MAC.
Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
COL
CRS
RX_CLK
RX_DV
RX_ER
RXD[3:0]
The following signals are used to transmit data from the MAC:
TX_CLK
TX_EN
TXD[3:0]
The LXT972M Transceiver supplies both clock signals as well as separate outputs for carrier sense
and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
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