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參數(shù)資料
| 型號： | WJLXT972MLC.A4SE000 |
| 廠商： | CORTINA SYSTEMS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
| 封裝： | LEAD FREE, LQFP-48 |
| 文件頁數(shù)： | 37/94頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | WJLXT972MLC.A4SE000 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
42
Document Number: 302875-004
Revision Date: February 18, 2005
5.6.7
Loopback
The LXT972M Transceiver provides the following loopback functions:
Figure 11 shows LXT972M Transceiver loopback paths.
5.6.7.1
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0.
Data that the MAC (TXData) transmits loops back on the receive side of the MII (RXData).
Operational loopback is not provided for 100 Mbps links, full-duplex links, or when Register
16.8 = 1.
5.6.7.2
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT972M Transceiver. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is
internally looped back by the LXT972M Transceiver and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by
setting the following register bits:
Register bit 0.14 = 1 (Setting to enable loopback mode)
Register bit 0.8 = 1 (Setting for full-duplex mode)
Register bit 0.12 = 0. (Disable auto-negotiation.)
Figure 11. Intel
LXT972M Transceiver Loopback Paths
B3485-01
10T
Loopback
Digital
Block
MII
100X
Loopback
Analog
Block
Intel LXT972M Transceiver
Operational
Loopback
Test Loopback
TX
Driver
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