參數(shù)資料
型號(hào): WEDPNF8M722V-1015BI
廠(chǎng)商: WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi): 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA275
封裝: 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù): 9/43頁(yè)
文件大?。?/td> 1280K
代理商: WEDPNF8M722V-1015BI
17
1 7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M722V-XBX
T
TT
TTABLE
ABLE
5 - B
5 - BOT
OT
OTTOM
TOM
B
BB
B
BOOT
OOT
B
BB
B
BLLLLLOCK
OCK
S
SECTOR
ECTOR
A
ADDRES
DDRES
DDRESS
S
T
TT
TTABLE
ABLE
Sector Size
(x8) Address Range
Sector
A
A18
18
A
A17
17
A
A16
16
A
A15
15
A
A14
14
A
A13
13
A
A12
12
(Kbytes)
(In hexidecimal)
SA0
0
X
16
00000h-03FFFh
SA1
0
1
0
8
04000h-05FFFh
SA2
0
1
8
06000h-07FFFh
SA3
0
1
X
32
08000h-0FFFFh
SA4
0
1
X
64
10000h-1FFFFh
SA5
0
1
0
X
64
20000h-2FFFFh
SA6
0
1
X
64
30000h-3FFFFh
SA7
0
1
0
X
64
40000h-4FFFFh
SA8
0
1
0
1
X
64
50000h-5FFFFh
SA9
0
1
0
X
64
60000h-6FFFFh
SA10
0
1
X
64
70000h-7FFFFh
SA11
1
0
X
64
80000h-8FFFFh
SA12
1
0
1
X
64
90000h-9FFFFh
SA13
1
0
1
0
X
64
A0000h-AFFFFh
SA14
1
0
1
X
64
B0000h-BFFFFh
SA15
1
0
X
64
C0000h-CFFFFh
SA16
1
0
1
X
64
D0000h-DFFFFh
SA17
1
0
X
64
E0000h-EFFFFh
SA18
1
X
64
F0000h-FFFFFh
During an erase or program operation, the system may check
the status of the operation by reading the status bits on
FD7-0 and FD23-16 respectively. Standard read cycle tim-
ings and IFCC read specifications apply. Refer to “Write Op-
eration Status” for more information, and to “Flash AC Char-
acteristics” for timing diagrams.
PROGRAM AND ERASE OPERATION
STATUS
When the system is not reading or writing to the device, it
can place the device in standby mode. In this mode, cur-
rent consump-tion is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
FOE input.
The device enters the CMOS standby mode when the FCS1-
2 and RST pins are held at Vcc ±0.3V. (Note that this is a
more restricted voltage range than VIH.) If FCS
1-2 and RST
are held at VIH, but not within Vcc ± 0.3V the device will
be in the standby mode, but the standby current will be
greater. The device requires standard access time (tCE ) for
read access when the device is in either of these standby
STANDBY MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t ACC + 30 ns. The au-
tomatic sleep mode is independent of the FCS1-2, FWE,
and FOE control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. IF cc5 in the DC Characteristics table represents
the automatic sleep mode current specification.
AUTOMATIC SLEEP MODE
The RST pin provides a hardware method of resetting the
device to reading array data. When the RST pin is driven
low for at least a period of tRP or greater the device imme-
diately terminates any operation in progress, tristates all out-
put pins, and ignores all read/write commands for the dura-
tion of the RST pulse. The device also resets the internal state
machine to reading array data. The operation that was inter-
rupted should be reinitiated once the device is ready to ac-
cept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RST pulse. When
RST is held at Vss ± 0.3V, the device draws CMOS standby
current (IFCC4). If RST is held at VIL but not within Vss ±
RST: HARDWARE RESET PIN
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WEDPNF8M722V-1210BC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BI 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BM 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1212BC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package