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參數(shù)資料
| 型號： | WEDPNF8M722V-1015BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 21/43頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | WEDPNF8M722V-1015BI |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M722V-XBX
TOGGLE BIT ALGORITHM
1. Read toggle bit twice to detemine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as FD5 changes to 1.
See text.
FIG. 9
READING TOGGLE BITS FD6/FD2
Refer to Figure 9 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read FD7-FD0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on FD7-0 on the following
read cycle.
However, if after the initial two read cycles, the system de-
termines that the toggle bit is still toggling, the system also
should note whether the value of FD5 is high (see the sec-
tion on FD5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as the device has successfully
completed the program or erase operation. If it is still tog-
gling, the device did not complete the operation success-
fully, and the system must write the reset command to re-
turn to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and FD5 has not gone high. The
system may continue to monitor the toggle bit and FD5 through
successive read cycles, determining the status as described
in the previous paragraph. Alternatively, it may choose to per-
form other system tasks. In this case, the system must start at
the beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 9).
FD5: EXCEEDED TIMING LIMITS
FD5 will indicate whether the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions FD5 will produce a “1”. This is a failure
condition that indicates the program or erase cycle was not
successfully completed.
The FD5 failure condition may appear if the system tries to
program a “1” to a location that is previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation,
and when the operation has exceeded timing limits, the
FD5 bit will produce a “1”.
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1015BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1212BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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