參數(shù)資料
型號(hào)： WEDPNF8M722V-1015BI
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 20/43頁(yè)
文件大?。?/td> 1280K
代理商： WEDPNF8M722V-1015BI
27
2 7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M722V-XBX
“Toggle Bit I” on FD6/22 indicates whether an Embedded
Program or Erase Algorithm is in progress or has been com-
pleted, or whether the device has entered the Erase Sus-
pend mode. Toggle Bit I may read at any address, and is
valid after the rising edge of the final FWE pulse in the com-
mand sequence (prior to the program or erase operation),
and during the sector erase time-out.
During an Embedded Program or Erase Algorithm opera-
tion, successive read cycles to any address will result in
FD6 toggling. (The system may use either FOE or FCS1-2 to
control the read cycles.) When operation is complete, FD6/
22 stop toggling.
After the erase command sequence is written, if all sectors
selected for erasing are protected, FD6/22 toggles for ap-
proximately 100s, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
Algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use FD6/22 and FD2/FD18 respectively, to-
gether to determine whether a sector is actively erasing or
and FD23-16 respectively on the
following read cycles. This
because FD7 may change asynchronously with FD0-6 and
FD16-22 respectively while Flash Output Enable (FOE) is
asser ted low. Figure 14, Data Polling timings (During Embed-
ded algorithms), in the “Flash AC characteristics” section
illustrates this.
Table 8 shows the outputs for Data Polling on FD7/FD23.
Figure 8 shows the Data Polling algorithm.
RY/BY1-2: READY/BUSY
The RY/BY1-2 is a dedicated, open drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY1-2 status is valid after the rising edge
of the final FWE pulse in the command sequence.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase Sus-
pend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Sus-
pend mode.), or is in the standby mode.
Table 8 shows the outputs for RY/BY1-2. Figures 11, 12, 13,
19 show RY/BY1-2 for read, program, erase and reset op-
erations, respectively.
FD6/22: TOGGLE BIT I
is erase-suspended. When the device is actively erasing (that
is, the Embedded Erase Algorithm is in progress) FD6/22
toggles. When the device enters the Erase Suspend mode,
FD6 stops toggling. However, the system must also use FD2
to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use FD7 (see the subsection
on “FD7: Data Polling”).
If a program address falls within a protected sector, FD6
also toggles for approximately 1s after the program com-
mand sequence is written, then returns to reading array data.
FD6 also toggles during erase-suspend-program mode, and
stops toggling once the Embedded Program algorithm is
complete.
Table 8 shows the outputs for “Toggle Bit I” on FD6. Figure
9 shows the Toggle Bit Algorithm. Figure 21 shows the toggle
bit timing diagrams. Figure 20 shows the difference between
FD2 and FD6 in graphical form. See also the subsection on
“FD2: Toggle Bit II”.
FD2: TOGGLE BIT II
The “Toggle Bit II” on FD2, when used with FD6, indicates
whether a particular sector is actively erasing (that is, the Em-
bedded Erase Algorithm is in progress) or whether that sec-
tor is erase-suspended. “Toggle Bit II” is valid after the rising
edge of the final FWE pulse in the command sequence.
FD2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either FOE or FCS to control the read
cycles.) FD2 cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. FD6, by comparison,
indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector
and mode information. Refer to Table 8 to compare out-
puts for FD2 and FD6.
Figure 9 shows the Toggle Bit Algorithm in flowchart form,
and the section “FD2: Toggle Bit II” explains the algorithm.
See also the subsection on “FD6: Toggle Bit I”. Figure 21
shows the toggle bit timing diagrams. Figure 20 shows the
difference between FD2 and FD6 in graphical form.
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WEDPNF8M722V-1015BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1212BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
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