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參數(shù)資料
| 型號： | WEDPNF8M722V-1015BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 41/43頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | WEDPNF8M722V-1015BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M722V-XBX
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
134, 217, 728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the star ting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 64MB SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2
n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
The 64MB SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,2,3,4)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Max
Units
SDRAM Operating Current: Active Mode;
ICC1
750
mA
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (5, 6, 7); FCS = High
SDRAM Standby Current: Active Mode; CKE = HIGH; CS = HIGH; FCS = High;
ICC3
250
mA
All banks active after tRCD met; No accesses in progress (5, 7, 8)
SDRAM Operating Current: Burst Mode; Continuous burst; FCS = High
ICC4
750
mA
Read or Write; All banks active; CAS latency = 3 (5, 6, 7)
SDRAM Self Refresh Current; FCS = High (14)
ICC7
10
mA
Flash VCC Active Current for Read : FCS = VIL, FOE = VIH, f = 5MHz (9, 13); CS = High, CKE = Low
IFCC1
45
mA
Flash VCC Active Current for Program or Erase: FCS = VIL, FOE = VIH (10, 13); CS = High, CKE = Low
IFCC2
80
mA
Standby Current: VCC = Max, CS = High, CKE = Low, FCS = VIH (13)
IFCC3
80
mA
NOTES:
1. All voltages referenced to VSS.
2. An initial pause of 100ms is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC must
be powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
3. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point.
4. ICC specifications are tested after the device is properly initialized.
5. ICC is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
6. The ICC current will decrease as the CAS latency is reduced. This is due to the
fact that the maximum cycle rate is slower as the CAS latency is reduced.
7. Address transitions average one transition every two clocks.
8. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL levels.
9. The ICC current listed includes both the DC operating current and the
frequency dependent component (at 5 MHz). The frequency component
typically is less than 8 mA/MHz, with OE at VIH.
10. ICC active while Embedded Algorithm (program or erase) is in progress.
11. Maximum ICC specifications are tested with VCC = VCC Max.
12. Automatic sleep mode enables the low power mode when addressed
remain stable for tacc + 30 ns.
13. SDRAM inactive and Power Down mode, all banks idle.
14. Self refresh available in commercial and industrial temperatures only.
SDRAM DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1015BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1212BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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