參數(shù)資料
型號: WEDPN8M64V-133B2C
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 8M X 64 SYNCHRONOUS DRAM, 5.5 ns, PBGA219
封裝: 21 X 21 MM, PLASTIC, BGA-219
文件頁數(shù): 15/15頁
文件大?。?/td> 398K
代理商: WEDPN8M64V-133B2C
WEDPN8M64V-XB2X
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
January 2005
Rev. 2
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indenite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is dened as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
*Self Refresh available in commercial and industrial temperatures only.
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