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參數(shù)資料
| 型號(hào)： | WEDPN8M64V-133B2C |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 8M X 64 SYNCHRONOUS DRAM, 5.5 ns, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大小： | 398K |
| 代理商： | WEDPN8M64V-133B2C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
WEDPN8M64V-XB2X
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
January 2005
Rev. 2
NOTES:
1.
For full-page accesses: y = 512.
2.
For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting
column within the block.
3.
For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting
column within the block.
4.
For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
5.
For a full-page burst, the full row is selected and A0-8 select the starting column.
6.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7.
For a burst length of one, A0-8 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
TABLE 1 – BURST DEFINITION
FIGURE 3 – MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1 A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
length is set to eight. The remaining (least signicant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
BURST TYPE
Accesses within a given burst may be programmed to be
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A 0-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M64V-133B2I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-133B2M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-133BC | 制造商:Microsemi Corporation 功能描述:8M X 64 SDRAM MODULE, 3.3V, 133 MHZ, 219 PBGA 25MM X 25MM, C - Bulk |
| WEDPN8M64VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN8M64V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
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