- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140355 > WED3DL644V10BC (WHITE ELECTRONIC DESIGNS CORP) 4M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA153 PDF資料下載
參數(shù)資料
| 型號： | WED3DL644V10BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA153 |
| 封裝： | 17 X 23 MM, BGA-153 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 918K |
| 代理商： | WED3DL644V10BC |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL644V
August 2005
Rev. 6
FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3,
BURST LENGTH=1
RAS#
CAS#
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE#
Cb
Cc
Rb
Ca
Ra
DQ
Row Active
Precharge
Read
Write
Read
Row Active
Db
Qc
WE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
tRCD
tRP
tRAS
tRCD
BS
Note 3
Note 4
Rb
Note 3
Note 2, 3
Note 2
Note 4
Note 2, 3
Ra
BS
Qa
tOH
tSAC
tSLZ
tRAC
tSS
tSH
tCCD
tCH
tCL
tCC
DON'T CARE
Note 2
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
tSS
tSH
3. Enable and disable auto precharge function are controlled by A10/AP in read/write
command.
4.
A10/AP and BA0~BA1 control bank precharge when precharge command is
asserted.
NOTES:
1.
All input except CKE & DQM can be don't care when CE# is high at the CK
high going edge.
2.
Bank active & read/write are controlled by BA0~BA1.
A10/AP
BA0
BA1
Operation
0
Distribute auto precharge, leave bank A active at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
Disable auto precharge, leave bank D active at end of burst.
1
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
Enable auto precharge, precharge bank D at end of burst.
A10/AP
BA0
BA1
Precharge
0
Bank A
0
1
Bank B
0
1
0
Bank C
0
1
Bank D
1
x
All Banks
BA0
BA1
Active & Read/Write
0
Bank A
0
1
Bank B
1
0
Bank C
1
Bank D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W29GL032CT7A | 2M X 16 FLASH 3V PROM, 80 ns, PBGA48 |
| WME128K8-150CCA | 128K X 8 EEPROM 5V, 150 ns, CDIP32 |
| WMS512K8VL-100DECEA | 512K X 8 STANDARD SRAM, 100 ns, CDSO32 |
| WMS512K8VL-85DECE | 512K X 8 STANDARD SRAM, 85 ns, CDSO32 |
| WF2M32B-90HM5A | 8M X 8 FLASH 5V PROM MODULE, 90 ns, CPGA66 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED3DL644V10BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx64 SDRAM |
| WED3DL644V7BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx64 SDRAM |
| WED3DL644V7BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx64 SDRAM |
| WED3DL644V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx64 SDRAM |
| WED3DL644V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx64 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。