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參數(shù)資料
| 型號(hào)： | WE904 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 0.1 - 1GHx Single Chip FM Transceiver |
| 中文描述： | 0.1 - 1GHx單芯片F(xiàn)M收發(fā)器 |
| 文件頁數(shù)： | 19/39頁 |
| 文件大?。?/td> | 623K |
| 代理商： | WE904 |
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Winceiver WE904/WE905
WiNEDGE & WiRELESS
0.1 - 1GHz Single Chip FM Transceiver
2003 WiNEDGE & WiRELESS PTE LTD
Page 26
Rev Date: 2003 May 27
SERIAL PROGRAMMING INTERFACE
Tx/Rx frequencies, reference frequency, as well as various operational and test modes are controlled
by a 3-wire serial bus comprised of Clock, Load Enable and Data. The programming word contains 23
bits. The first two bits (LSB) select the programming of the register for receive VCO frequency,
transmit VCO frequency, reference frequency or device operational modes. The remaining bits
contain the data to be programmed. The timing diagram below shows the relationship between Data,
Clock, and Load Enable.
23
22
21
20
19
............... 6
5
4
3
2
1
Data is clocked into the internal shift registers on the positive edge of the CLOCK (pin 3), while Load
Enable (pin 1) is held HIGH. Data is loaded from the shift registers into the data registers on the
negative edge of the Load Enable (LE). This load is NOT synchronized with the programmable
divider, i.e. the load is controlled directly by the negative falling edge of the Load Enable.
TIMING DIAGRAM
tds tdh
DATA
tld
tlg
CLOCK
LE
MSB
LSB
tds:
Data set up time before +ve CLOCK edge
30ns min
tdh:
Data hold time after +ve CLOCK edge
30ns min
tld:
Latch Enable lead time before first +ve CLOCK edge.
30ns min
tlg:
Latch Enable lag time after last +ve CLOCK edge.
30ns min
CLOCK
LE
DATA
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WE905 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:0.1 - 1GHx Single Chip FM Transceiver |
| WE9104 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pulse Telephone Dialer |
| WE9110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pulse Telephone Dialer |
| WE9140 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:TONE/PULSE SWITCHABLE DIALER WITH REDIAL |
| WE9140A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:TONE/PULSE SWITCHABLE DIALER WITH REDIAL |
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