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| 型號： | W986416BH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 42/42頁 |
| 文件大?。?/td> | 2061K |
| 代理商： | W986416BH-7 |
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W986416BH
1M x 16 bit x 4 Banks SDRAM
Revision 1.4
Publication Release Date: July, 1999
- 9 -
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth
table for the operation commands.
Table 1 Truth Table
( note (1) , (2) )
command
Device state
CKEn-1
CKEn
DQM
BS0,1
A10
A11,
A9-0
CS
RA
CAS
WE
Bank Active
Idle
H
x
v
L
H
Bank Precharge
Any
H
x
v
L
x
L
H
L
Precharge All
Any
H
x
H
x
L
H
L
Write
Active (3)
H
x
v
L
v
L
H
L
Write with Autoprecharge
Active (3)
H
x
v
H
v
L
H
L
Read
Active (3)
H
x
v
L
v
L
H
L
H
Read with Autoprecharge
Active (3)
H
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
v
L
No - Operation
Any
H
x
L
H
Burst Stop
Active (4)
H
x
L
H
L
Device Deselect
Any
H
x
H
x
Auto - Refresh
Idle
H
x
L
H
Self - Refresh Entry
Idle
H
L
x
L
H
Self Refresh Exit
idle
(S.R.)
L
H
x
H
L
x
H
x
H
x
Clock suspend Mode Entry
Active
H
L
x
Power Down Mode Entry
Idle
Active (5)
H
L
x
H
L
x
H
x
H
x
Clock Suspend Mode Exit
Active
L
H
x
Power Down Mode Exit
Any
(power down)
L
H
x
H
L
x
H
x
H
x
Data write/Output Enable
Active
H
x
L
x
Data Write/Output Disable
Active
H
x
H
x
Notes: (1) v= valid x = Don't care L= Low Level H= High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
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