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參數(shù)資料
| 型號： | W9812G21H-6I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-86 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | W9812G21H-6I |
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W9812G2IH
Publication Release Date:Nov. 06, 2008
- 17 -
Revision A01
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC Test Load diagram.
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
30pF
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
(The tT maximum can’t be more than 10nS for low frequency application.)
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
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PDF描述 |
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| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| W9812G6JH-6 | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| W986416AH-10 | 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| W986432DH-6 | 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W986432DH-8 | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9812G2GB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words 】 4 banks 】 32 bits |
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