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參數(shù)資料
| 型號： | W9812G21H-6I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-86 |
| 文件頁數(shù)： | 36/36頁 |
| 文件大小： | 1422K |
| 代理商： | W9812G21H-6I |
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W9812G2IH
Publication Release Date:Nov. 06, 2008
- 9 -
Revision A01
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency
in a burst read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page
burst write operation, then any residual data from the burst write cycle will be ignored.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
相關(guān)PDF資料 |
PDF描述 |
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| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| W9812G6JH-6 | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| W986416AH-10 | 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| W986432DH-6 | 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W986432DH-8 | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9812G2GB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words 】 4 banks 】 32 bits |
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