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參數(shù)資料
| 型號： | W78M64110SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 50/50頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | W78M64110SBC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
valid data, the data outputs on DQ6-DQ0 may be still invalid.
Valid data on DQ7-D00 appears on successive read cycles.
See the following for more information: Table 18, shows the
outputs for Data# Polling on DQ7. FIG: 7, shows the Data#
Polling algorithm; and FIG: 22, shows the Data# Polling timing
diagram.
DQ6: TOGGLE BIT I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the nal WE# pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address that is being
programmed or erased causes DQ6 to toggle. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 1μs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program Algorithm
is complete.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-
asserted and reasserted to show the change in state.
DQ2: TOGGLE BIT II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the nal WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 18 to compare outputs for DQ2
and DQ6.
READING TOGGLE BITS DQ6/DQ2
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the rst read. After the second read, the system would
compare the new value of the toggle bit with the rst. If
the toggle bit is not toggling, the device has completed
the program or erases operation. The system can read
array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see
DQ5: Exceeded Timing Limits). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erases
operation. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data. The
remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high.
The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation. Refer to
FIG: 7 for more details.
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