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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 39 MEMORY ARRAY COMMAND DEFINITIONS
Command
Cycles
Bus Cycles (Note 1-5)
First
Second
Third
Fouth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (6)
1
RA
RD
Reset (7)
1
XXX
F0
AutoSelect
(8,
9)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID (8)
4
555
AA
2AA
55
555
90
X01
227E
X0E
(8)
X0F
(8)
Sector Protect Verify (10)
4
555
AA
2AA
55
555
90
[SA]X02
(10)
Secure Device Verify (11)
4
555
AA
2AA
55
555
90
X03
(11)
CFI Query (12)
1
55
98
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer
3
555
AA
2AA
55
SA
25
SA
WC
WBL
PD
WBL
PD
Program Buffer to Flash (Conrm)
1
SA
29
Write-to-Buffer-Abort Reset
3
555
AA
2AA
55
555
F0
Unlock
Bypass
Enter
3
555
AA
2AA
55
555
20
Program (14)
2
XXX
A0
PA
PD
Sector Erase (14)
2
XXX
80
SA
30
Chip Erase (14)
2
XXX
80
XXX
10
Reset (15)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend/Program Suspend (16)
1
XXX
B0
Erase Resume/Program Resume (17)
1
XXX
30
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured SIlicon Sector Exit (18)
4
555
AA
2AA
55
555
90
XX
00
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling
edge of the WE# or CE# pulse, whichever happens later.
Notes
1.
See Table 2 for description of bus operations.
2.
All values are in hexadecimal.
3.
All bus cycles are write cycles unless otherwise noted.
4.
Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5.
Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA
or PA required. (AMAX is the Highest Address pin.).
6.
No unlock or command cycles required when reading array data.
7.
The Reset command is required to return to reading array data when device is in the
autoselect mode, or if DQ5 goes high (while the device is providing status data).
8.
See Table 3 for device ID values and denitions.
9.
The fourth, fth, and sixth cycles of the autoselect command sequence are read
cycles.
10. The data is 00h for an unprotected sector and 01h for a protected sector. See
Autoselect for more information. This is same as PPB Status Read except that the
protect and unprotect statuses are inverted here.
11. The data value for DQ7 is “1” for a serialized, protected Secured Silicon Sector region
and “0” for an unserialized, unprotected region. See data and denitions.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or
CE# pulse, whichever happens rst.
SA = Address of the sector to be veried (in autoselect mode) or erased. Address bits
Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as
PA.
WC = Word Count is the number of write buffer locations to load minus 1.
12. Command is valid when device is ready to read array data or when device is in
autoselect mode.
13. Command sequence returns device to reading array after being placed in a Write-to-
Buffer-Abort state. Full command sequence is required if resetting out of abort while
in Unlock Bypass mode.
14. The Unlock-Bypass command is required prior to the Unlock-Bypass- Program
command.
15. The Unlock-Bypass-Reset command is required to return to reading array data when
the device is in the unlock bypass mode.
16. The system can read and program/program suspend in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
17. The Erase Resume/Program Resume command is valid only during the Erase
Suspend/Program Suspend modes.
18. The Exit command returns the device to reading the array.