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參數(shù)資料
| 型號： | W78CE354P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 顯示器單片機 |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 426K |
| 代理商： | W78CE354P |
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W78C354
- 26 -
I. Timer/Counter
The W78C354 has two 16-bit timer/counters, Timer/counter 0 and Timer/counter 1, which are
identical with those on the standard 80C32, and one 8-bit auto-reload timer. Once the "MOV
AUTOLOAD, #data" instruction is executed, the auto-reload timer will load the specified data and
start to count. If the TIMEOUT bit in INTMSK is set, the auto-reload timer will periodically generate an
interrupt to the CPU.
The auto-reload timer interval is programmable:
Minimum timer interval = 1/(F
CLOCK
ò
1024)
Desired timer interval = Minimum interval
×
[(preset value of the AUTOLOAD)+1]
Maximum timer interval = Minimum interval
×
255
AUTOLOAD: 8-bit auto-reload timer register which stores preset value.
16 MHz
18.432 MHz
20 MHz
Minimum Interval
64
μ
S
16.3 mS
55
μ
S
14.2 mS
51.2
μ
S
13.1 mS
Maximum Interval
J. Parabola Interrupt Generator
The parabola interrupt generator is a 16-bit binary count-up auto-reload timer that is used to generate
the parabola interrupt to the W78C354 for loading parabola waveform data to dynamic DACs. It
periodically generates an interrupt by setting the PARAINT bit in INTMSK, if the "MOV PARAL, #Low
byte data" and "MOV PARAH, #High byte data" instructions are executed.
The parabola interrupt generator period is programmable:
Time base = 1/F
CLOCK
Desired interrupt period = Time base
×
{[preset value of the (PARAH, PARAL)]+1}
Maximum period = Time base
×
65535
PARAL: Parabola interrupt generator register that stores low byte preset value
PARAH: Parabola interrupt generator register that stores high byte preset value
K. 6-bit A/D Converter
The 6-bit analog-to-digital converter uses the successive approximation method to convert one of the
four analog input channels into a digital data value. The A/D converter resolution is
±
1 LSB, and the
conversion time is 100 usec. The result is read from SFR ADC.
Bit-pairs (ADCS1, ADCS2) in SFR CONTREG1 are used to select one of the four channels as the
analog input (see Table 3). Conversion is started by setting the bit ADCSTRT in CONTREG1 by
software. When the A/D conversion is completed, the ADCSTRT bit is automatically cleared by
hardware to stop the A/D converter's operation, and the ADCINT bit in INTVECT is set by hardware at
the same time. To enable the A/D converter interrupt, set the ADCINT bit in INTMSK.
Table 4. Select A/D converter channel
(ADCS1, ADCS0)
Selected channel
(0, 0)
ADC0
(0, 1)
ADC1
(1, 0)
ADC2
(1, 1)
ADC3
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