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參數(shù)資料
| 型號(hào)： | W78CE354P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 顯示器單片機(jī) |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 426K |
| 代理商： | W78CE354P |
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W78C354
Publication Release Date: October 1996
- 21 -
Revision A1
Table 3. Serial clock rates
BIT FREQUENCY (KHz) AT THE SCL
PIN
CR2
CR1
CR0
16 MHz
18.432 MHz
20 MHz
FORMULA
0
0
0
63
72
78
F
OSC
/256
0
0
1
71
82
89
F
OSC
/224
0
1
0
83
96
-
F
OSC
/192
0
1
1
100
-
-
F
OSC
/160
1
0
0
17
19
20
F
OSC
/960
1
0
1
-
-
-
F
OSC
/120
1
1
0
-
-
-
F
OSC
/60
G-1.10 S1STA (SIO1 Status Register) (D9H)
The newly added SFR S1STA is an 8-bit read-only register. The three least significant bits are always
zero. The five most significant bits contain the status code. There are 26 possibile status codes.
When the S1STA contains F8H, no serial interrupt is requested. All other the S1STA values
correspond to defined SIO1 states (refer to the Philips specification for the I
2
C bus). When each of
these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in the
S1STA one machine cycle after the bit SI is set by hardware and is still present one machine cycle
after the bit SI has been reset by software.
G-2 DDC1 Port
DDC1 is a serial output port that supports DDC1 communication. After the DDC1 control circuit loads
the next data byte from the data buffer to the shift register and generates a DDC1INT signal to the
CPU, eight data bits and one zero (for the "acknowledge" signal) are shifted out to the DSDA pin
sequentially on each rising edge of the VIN signal. In the interrupt service routine, the W78C354
should fetch the next byte of EDID data and write it to SFR DDC1. If the bit ENDDC1 of SFR
CONTREG1 is cleared to zero, the shift register is stopped, and the DSDA output is kept high.
One DDC1 port to support DDC1; ENDDC1 must be set to 1.
One SIO1 port support DDC2B/2B+; ENDDC1 must be set to 0.
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