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參數(shù)資料
| 型號(hào)： | W78CE354P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 顯示器單片機(jī) |
| 文件頁數(shù)： | 19/44頁 |
| 文件大小： | 426K |
| 代理商： | W78CE354P |
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W78C354
Publication Release Date: October 1996
- 19 -
Revision A1
7
6
5
4
3
2
1
0
S1ADR
X
X
X
X
X
X
X
-
|--------------- Address that owns slave ---------------|
G-1.2 S1DAT (SIO1 Data Register) (DBH)
This register contains a byte of serial data that is waiting to be transmitted or has just been received.
When the W78C354 is not performing a shifting operation, data can be read from or written to SFR
S1DAT. Data in the S1DAT remain stable as long as SI is set. Data in the S1DAT are shifted from the
most significant bit to the least significant bit, and while data are being shifted out, data on the bus
are simultaneously being shifted in. S1DAT always contains the last data byte present on the bus.
Thus, if arbitration is lost, the transition from master transmitter to slave receiver is made with the
correct data in S1DAT.
7
6
5
4
3
2
1
0
S1DAT
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
LSB
MSB
Eight bits of data in the S1DAT are shifted out or in, followed by an acknowledge bit. The
acknowledge (ACK) bit is controlled by the SIO1 port hardware and cannot be accessed by the
W78C354. Serial data are shifted through the ACK flag into S1DAT on the rising edges of the serial
clock pulses on the SCL line and are shifted out from the S1DAT on the falling edges of the SCL
clock pulse. When a byte has been shifted into the S1DAT, the serial data are available in S1DAT,
and the acknowledge bit is returned by the control logic during the ninth clock pulse.
G-1.3 S1CON (SIO1 Control Register) (D8H)
The newly added SFR S1CON can be read or written by the programmer. Two bits (SI and STO) are
affected by the SIO1 port hardware. When a serial interrupt is requested, the bit SI is automatically
set, and when a stop condition is present on the bus, the bit STO is cleared. The bit STO is also
cleared when ENS1 = "0."
7
6
5
4
3
2
1
0
S1CON
CR2 ENS1 STA
STO
SI
AA
CR1
CR0
G-1.4 ENS1 (SIO1 Enable Bit)
When the bit ENS1 is "0," the SDA and SCL outputs are in a high impedance state, the SIO1 port is
in the "not addressed" slave mode, and no other bits are affected, except that the bit STO in S1CON
is forced to "0." P1.2 and P1.3 may be used as open drain I/O pins.
When ENS1 is "1," SIO1 is enabled. The P1.2 and P1.3 pins must be set to high.
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