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參數(shù)資料
| 型號(hào)： | W78CE354P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 顯示器單片機(jī) |
| 文件頁(yè)數(shù)： | 10/44頁(yè) |
| 文件大?。?/td> | 426K |
| 代理商： | W78CE354P |
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W78C354
- 10 -
4. Interrupt Priority Register (IP)
BIT
NAME
FUNCTION
IP.7
-
(Reserved)
IP.6
-
(Reserved)
IP.5
*1
Define the DDC port's I
2
C interrupt priority level.
If IP.5 = 1, the priority level is higher.
IP.4
PS
Define the serial port interrupt priority level.
If PS = 1, the priority level is higher.
IP.3
PT1
Define the Timer 1 interrupt priority level.
If PT1 = 1, the priority level is higher.
IP.2
*1
Define the *2 priority level.
If IP.2 = 1, the priority level is higher.
IP.1
PT0
Define the Timer 0 interrupt priority level.
If PT0 = 1, the priority level is higher.
IP.0
PX0
Define the external interrupt 0 priority level.
If PX0 = 1, the priority level is higher.
Notes:
*1. No name for ASSEMBLER, must be used via "IP.x".
*2. DSCLINT+ADCINT+TIMEOUT+SOAINT+VEVENT+PARAINT+DDC1INT.
C. Newly Added Special Function Registers
In addition to the 80C32 SFRs, the W78C354 has forty-nine new SFRs in the SFR address space, as
listed in Table 2.
Table 2. New special function registers
REGISTER
ADDRESS
FUNCTION
LENGTH
R/W
TYPE
RESET
CONTENT
1
2
3
4
5
6
7
8
9
10
11
12
CONTREG1
CONTREG5
CONTREG2
PARAL
PARAH
AUTOLOAD
DHREG
DVREG
DDC1
INTMSK
BDDAC
DBRM
80H
84H
85H
8EH
8FH
91H
92H
93H
94H
95H
96H
97H
Control register 1, bit-addressable
Control register 5
Control register 2
Parabola interrupt generator low byte register
Parabola interrupt generator high byte register
8-bit auto-reload timer register
Dummy Hsync frequency generator register
Dummy Vsync frequency generator register
DDC port's DDC1 data buffer
Interrupt mask register
8-bit PWM register for 12-bit PWM/BRM dynamic DAC
4-bit BRM register for 12-bit PWM/BRM dynamic DAC
8
8
8
8
8
8
4
8
8
8
8
4
R/W
R/W
W
W
W
W
W
W
W
W
W
W
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
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