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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-78 -
D4/35
R/W
B2_EXIM
B2 channel extended interrupt mask
D8/36
R
B2_STAR
B2 channel status register
DC/37
R/W
B2_ADM1
B2 channel address mask 1
E0/38
R/W
B2_ADM2
B2 channel address mask 2
E4/39
R/W
B2_ADR1
B2 channel address 1
E8/3A
R/W
B2_ADR2
B2 channel address 2
EC/3B
R
B2_RBCL
B2 channel receive frame byte count low
F0/3C
R
B2_RBCH
B2 channel receive frame byte count high
B8/2E
R/W
B2_IDLE
B2 channel transmit idle pattern
TABLE 8.6 REGISTER SUMMARY: B2 CHANNEL HDLC
Offset R/W
Name
7
6
5
4
3
2
1
0
C0/30 R
B2_RFIFO
C4/31 W
B2_XFIFO
C8/32 R/W
B2_CMDR
RACK
RRST
RACT
XACTB
XMS
XME
XRST
CC/33 R/W
B2_MODE
MMS
ITF
EPCM
B2_SW1
B2_SW0
SW56
FTS1
FTS0
D0/34 R_clr B2_EXIR
RMR
RME
RDOV
XFR
XDUN
D4/35 R/W
B2_EXIM
RMR
RME
RDOV
XFR
XDUN
D8/36 R
B2_STAR
RDOV
CRCE
RMB
XDOW
XBZ
DC/37 R/W
B2_ADM1
MA17
MA16
MA15
MA14
MA13
MA12
MA11
MA10
E0/38 R/W
B2_ADM2
MA27
MA26
MA25
MA24
MA23
MA22
MA21
MA20
E4/39 R/W
B2_ADR1
RA17
RA16
RA15
RA14
RA13
RA12
RA11
RA10
E8/3A R/W
B2_ADR2
RA27
RA26
RA25
RA24
RA23
RA22
RA21
RA20
EC/3B R
B2_RBCL
RBC7
RBC6
RBC5
RBC4
RBC3
RBC2
RBC1
RBC0
F0/3C R
B2_RBCH
LOV
RBC12
RBC11
RBC10
RBC9
RBC8
B8/2E R/W
B2_IDLE
IDLE7
IDLE6
IDLE5
IDLE4
IDLE3
IDLE2
IDLE1
IDLE0
The B2 channel HDLC register's definitions and functions are the same as those of B1 channel HDLC. Please refer to section
8.2 for a detailed description.
8.4 PCI Configuration Register
W6692A provides PCI interface for PCI-based system and only supports slave mode. There are two optional Base Address
Registers (Memory or I/O) for host access to W6692A internal registers.
Reads to reserved or unimplemented registers return data value of 0. Write to these registers are completed normally and the
data are discarded.