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參數(shù)資料
| 型號(hào)： | W6692ACF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 50/98頁 |
| 文件大小： | 584K |
| 代理商： | W6692ACF |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-54 -
This bit indicates the status of layer 1 D channel.
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
Note : Due to design mistake, DRDY=1 does not mean S/T layer 1 is in F7 state. Software has to check “DRDY=1 and C/I
code=AI8/10” in order to transmit.
8.1.11 D_ch Receive Status Register
D_RSTA
Read
Address 28H/0AH
Value after reset: 20H
7
6
5
4
3
2
1
0
RDOV
CRCE
RMB
0
RDOV
Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV = 1. The frame overflow condition will not set this bit.
CRCE
CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB
Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset
the receiver.
Note: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12
D_ch SAPI Address Mask
D_SAM
Read/Write
Address 2CH/0BH
Value after reset: 00H
7
6
5
4
3
2
1
0
SAM7
SAM6
SAM5
SAM4
SAM3
SAM2
SAM1
SAM0
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit is "1" the corresponding
bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with SAPG is always performed.
Note : For the LAPD frame, the least significant two bits are the C/R bit and EA =0 bit. It is suggested that the comparison
with C/R bit be masked. EA=0 for two octet address frame e.g LAPD, EA=1 for one octet address frame.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6694ACD | DATACOM, ISDN CONTROLLER, PQFP48 |
| W671320P | TELECOM-SLIC, PQCC28 |
| W671361P | TELECOM-SLIC, PQCC28 |
| W671361Y | TELECOM-SLIC, QCC32 |
| W671310P | TELECOM-SLIC, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W66ARX-18 | 制造商:Magnecraft 功能描述: |
| W66MAF185X | 制造商:Panasonic Industrial Company 功能描述:CRT |
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