參數(shù)資料
型號(hào)： W6692ACD
英文描述： ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料
文件頁數(shù)： 67/101頁
文件大?。?/td> 851K
代理商： W6692ACD
W6692A
Publication Release Date: July 2000
- 67 -
Revision A1
8.1.38 Monitor Channel 1 Interrupt Register MO1I Read_clear Address 75H/42H
Value after reset: 00H
7
6
5
4
3
2
1
0
MDR1
MER1
MDA1
MAB1
MDR1
Monitor channel 1 Data Receive
MER1
Monitor channel 1 End of Reception
MDA1
Monitor channel 1 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
MAB1
Monitor channel 1 Data Abort
8.1.39 Monitor Channel 1 Control Register
MO1C Read/Write
Address 79H/43H
Value after reset: 00H
7
0
6
0
5
0
4
0
3
2
1
0
MRIE1
MRC1
MXIE1
MXC1
MRIE1 Monitor Channel 1 Receive Interrupt Enable
Monitor channel interrupt status MDR1, MER1 generation is enabled (1) or masked (0).
MRC1 MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR1 interrupt is blocked, except for the first byte of a
packet (if MRE = 1).
1: MR internally controlled by the W6692A according to Monitor channel protocol. In addition, the
MDR1 interrupt is enabled for all received bytes according to the Monitor channel protocol (if
MRE = 1).
MXIE1 Monitor channel 1 Transmit Interrupt Enable
Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0).
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