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W6692A
Publication Release Date: July 2000
- 59 -
Revision A1
CODR3-0 Layer 1 Indication Code
Value of the received layer 1 indication code. Note these bits have a buffer size of two.
Note
: If S/T layer 1 function is disabled and GCI slave mode is enabled (GMODE = 1 in GCR register), CIR register is used to
receive layer 1 indication code from U transceiver. In this case, SCC bit is not used and the supported indication codes are:
Indication
Symbol
Code
Descriptions
Deactivation confirmation
DC
1111
Idle code on GCI interface
Power up indication
PU
0111
U transceiver power up
8.1.24 Command/Indication Transmit Register
CIX
Read/Write
Address 5CH/17H
Value after reset: 0FH
7
6
5
4
3
2
1
0
CODX3 CODX2 CODX1 CODX0
CODX3-0 Layer 1 Command Code
Value of the command code transmitted to layer 1.
A read to this register returns the previous written value.
Note
: If S/T layer 1 function is disabled and GCI slave mode is enabled (GMODE = 1 in GCR register), CIX register is used to issue
layer 1 command code to U transceiver. In this case, the supported command code is:
Command
Symbol
Code
Descriptions
Activate request command
AR
1000
Activate request command
8.1.25 S/Q Channel Receive Register SQR Read Address 60H/18H
Value after reset: XXH
7
6
5
4
3
2
1
0
XIND1
XIND0
MSYN
SCIE
S1
S2
S3
S4
XIND1 XINTIN1 Data
This bit reflects the current level of XINTIN1 pin.
XIND0 XINTIN0 Data
This bit reflects the current level of XINTIN0 pin.
MSYN Multiframe Synchronization
When this bit is "1", a multiframe synchronization is achived, i.e the S/T receiver has synchronized to
the received F
A
and M bit patterns.
SCIE
S Channel Change Interrupt Enable
This bit reflects the bit written in the SQX register.