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W6692A
- 52 -
An D_XFR interrupt is generated in the following cases:
- After an XMS command, when
≥
64 bytes of XFIFO is empty
- After an XMS together with an XME command is issued, when the whole frame has been
transmitted
- After an XRST command
- After hardware reset
XINT1 XINTIN1 Interrupt
This bit indicates that level change occurs at XINTIN1 pin. Both positive and negative edges will
cause an interrupt.
XINT0 XINTIN1 Interrupt
This bit indicates that level change occurs at XINTIN0 pin. Both positive and negative edges will
cause an interrupt.
D_EXI D_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in D_EXIR register.
B1_EXI B1_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in B1_EXIR register.
B2_EXI B2_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in B2_EXIR register.
Note
: A read of the ISTA register clears all bits except D_EXI, B1_EXI and B2_EXI bits. D_EXI bit is cleared when all bits in
D_EXIR register are cleared. B1_EXI bit is cleared by reading B1_EXI register and B2_EXI bit is cleared by reading B2_EXIR
register.
8.1.7 Interrupt Mask Register IMASK Read/Write
Address 18H/06H
Value after reset: FFH
7
6
5
4
3
2
1
0
D_RMR
D_RME
D_XFR
XINT1
XINT0
D_EXI
B1_EXI
B2_EXI
Setting the bit to "1" masks the corresponding interrupt source in ISTA register. Masked interrupt
status bits are read as zero. They are internally stored and pending until the mask bits are zero.
Setting the D_EXI, B1_EXI or B2_EXI bit to "1" masks all the interrupts in D_EXIR, B1_EXIR or
B2_EXIR register, respectively.
8.1.8 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 1CH/07H
Value after reset: 00H
7
6
5
4
3
2
1
0
0
RDOV
XDUN
XCOL
TIN2
GCI
ISC
T1EXP