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W6692A
Publication Release Date: July 2000
- 63 -
Revision A1
Monitor interrupt status MDA0, MAB0 generation is enabled (1) or masked (0).
MXC0 MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W6692A according to Monitor channel protocol.
8.1.32 GCI Mode Control/Status Register GCR Read/Write Address 7CH/1FH
Value after reset: 00H
7
6
5
4
3
2
1
0
MAC0
MAC1
GACT
TLP
GRLP
SPU
PD
GMODE
MAC0 Monitor Transmit Channel 0 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 0.
0: the previous transmission has been terminated. Before starting a transmission, the
microprocessor should verify that the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 0 (MO0X) register, the
microprocessor sets this bit to 1.
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data
(contents of MOX) in the correspond frame.
MAC1 Monitor Transmit Channel 1 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 1.
0: the previous transmission has been terminated. Before starting a transmission, the
microprocessor should verify that the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 1 (MO1X) register, the
microprocessor sets this bit to 1.
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data
(contents of MOX) in the correspond frame.
GACT GCI Switching Active
Determines which CODEC interface is to be activated in B channle switching. Valid only in GCI
master mode. In GCI slave mode, PCM ports are always enabled.
0: PCM ports are enabled
1: GCI bus is enabled.
TLP Test Loop
When this bit is set to 1 both the DU and DD lines are internally connected together. External input on
DD is ignored. Valid in GCI slave mode.