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參數(shù)資料
| 型號： | W3H32M72E-667SB2M |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封裝： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 1062K |
| 代理商： | W3H32M72E-667SB2M |
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
14
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
opened (activated), even when additive latency is used. This is
accomplished via the ACTIVE command, which selects both the
bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or
WRITE command may be issued to that row, subject to the tRCD
specication. tRCD (MIN) should be divided by the clock period and
rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or
WRITE command can be entered. The same procedure is used
to convert other specication limits from time units to clock cycles.
For example, a tRCD (MIN) specication of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.
A subsequent ACTIVE command to a different row in the same bank
can only be issued after the previous active row has been closed
(precharged). The minimum time interval between successive
ACTIVE commands to the same bank is dened by tRC.
A subsequent ACTIVE command to another bank can be issued
while the rst bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between
successive ACTIVE commands to different banks is dened by tRRD
READ COMMAND
The READ command is used to initiate a burst read access to an
active row. The value on the BA1–BA0 inputs selects the bank,
and the address provided on inputs A0–i (where i = A9) selects
the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
READ OPERATION
READ bursts are initiated with a READ command. The starting
column and bank addresses are provided with the READ command
and auto precharge is either enabled or disabled for that burst
access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto
precharge is disabled, the row will be left open after the completion
of the burst.
During READ bursts, the valid data-out element from the starting
column address will be available READ latency (RL) clocks later.
RL is dened as the sum of AL and CL; RL = AL + CL. The value
for AL and CL are programmable via the MR and EMR commands,
respectively. Each subsequent data-out element will be valid
nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#).
DQS/DQS# is driven by the DDR2 SDRAM along with output data.
The initial LOW state on DQS and HIGH state on DQS# is known
as the read preamble (tRPRE). The LOW state on DQS and HIGH
state on DQS# coincident with the last data-out element is known
as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have
been initiated, the DQ will go High-Z.
FIGURE 10 – ACTIVE COMMAND
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Row
Bank
ADDRESS
BANK ADDRESS
FIGURE 11 – READ COMMAND
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Col
Bank
ADDRESS
BANK ADDRESS
AUTO PRECHARGE
ENABLE
DISABLE
A10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3H32M72E-667SBC | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| W3H64M16E-400BC | 64M X 16 DDR DRAM, 0.6 ns, PBGA79 |
| W3H64M64E-400SBC | 64M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H32M72E-667SB2M/T/R | 制造商:Microsemi Corporation 功能描述:PBGA,32M X72,DDR2 SDRAM, 1.8V - Tape and Reel |
| W3H32M72E-667SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-667SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-667SBM | 制造商:PMG/Microsemi 功能描述: |
| W3H32M72E-ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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