參數(shù)資料
型號: W3H128M72ER-667SBM
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM, 0.5 ns, PBGA255
封裝: 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255
文件頁數(shù): 7/34頁
文件大?。?/td> 1028K
代理商: W3H128M72ER-667SBM
W3H128M72ER-XNBX
15
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Function
CKE
CS#
RAS#
CAS#
WE#
BA2
BA1
BA0
A13
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
LLLL
BA
OP Code
2
REFRESH
H
L
H
XXXX
SELF-REFRESH Entry
H
L
H
XXXX
SELF-REFRESH Exit
LH
H
XXX
XXXX
7
L
HHH
Single bank precharge
HH
L
H
L
X
L
X
2
All banks PRECHARGE
HH
L
H
L
X
H
X
Bank activate
H
L
H
L
BA
Row Address
WRITE
HH
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
HH
L
H
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
LH
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
LH
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
XXXX
Device DESELECT
H
X
H
XXXXXXX
POWER-DOWN entry
HL
H
XXX
XXXX
4
L
HHH
POWER-DOWN exit
LH
H
XXX
XXXX
4
L
HHH
Note: 1. All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a dened logic level).
7. Self refresh exit is asynchronous.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
相關(guān)PDF資料
PDF描述
W3EG72126S262AJD3SG 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
W3EG72126S265JD3SG 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
W3H128M72E0533SBM DDR DRAM, PBGA208
W3H128M72E2-533NBC 128M X 72 DDR DRAM, 0.5 ns, PBGA208
W7NCF01GH10CS6CG 64M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H13C1048AT 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors
W3H13C1048AT1A 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體:
W3H13C1048AT1F 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體:
W3H15C1038AT 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors
W3H15C1038AT1A 功能描述:饋通電容器 50volt .01uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體: