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參數(shù)資料
| 型號(hào)： | W3H128M72ER-667SBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 0.5 ns, PBGA255 |
| 封裝： | 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | W3H128M72ER-667SBM |
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W3H128M72ER-XNBX
18
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
WRITE COMMAND
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA2–BA0 inputs
selects the bank, and the address provided on inputs A0–9
selects the starting column location. The value on input
A10 determines whether or not auto precharge is used.
If auto precharge is selected, the row being accessed
will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered
LOW, the corresponding data will be written to memory; if
the DM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed
to that byte/column location.
WRITE OPERATION
WRITE bursts are initiated with a WRITE command, as
shown in Figure 12. DDR2 SDRAM uses WL equal to RL
minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)].
The starting column and bank addresses are provided
with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst.
During WRITE bursts, the rst valid data-in element will
be registered on the rst rising edge of DQS following the
WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state
on DQS between the WRITE command and the rst rising
edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the
write postamble.
The time between the WRITE command and the rst rising
DQS edge is WL ± tDQSS. Subsequent DQS positive rising
edges are timed, relative to the associated clock edge, as
± tDQSS. tDQSS is specied with a relatively wide range (25
percent of one clock cycle). All of the WRITE diagrams
show the nominal case, and where the two extreme cases
(tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they
have also been included. Upon completion of a burst,
assuming no other commands have been initiated, the
DQ will remain High-Z and any additional input data will
be ignored.
Data for any WRITE burst may be concatenated with a
subsequent WRITE command to provide continuous ow
of input data. The rst data element from the new burst is
applied after the last element of a completed burst. The
new WRITE command should be issued x cycles after the
rst WRITE command, where x equals BL/2.
DDR2 SDRAM supports concurrent auto precharge
options, as shown in Table 4.
DDR2 SDRAM does not allow interrupting or truncating
any WRITE burst using BL = 4 operation. Once the BL
= 4 WRITE command is registered, it must be allowed
to complete the entire WRITE burst cycle. However,
a WRITE (with auto precharge disabled) using BL = 8
operation might be interrupted and truncated ONLY by
another WRITE burst as long as the interruption occurs
on a 4-bit boundary, due to the 4n prefetch architecture of
DDR2 SDRAM. WRITE burst BL = 8 operations may not
to be interrupted or truncated with any command except
another WRITE command.
Data for any WRITE burst may be followed by a subsequent
READ command. The number of clock cycles required to
meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data
for any WRITE burst may be followed by a subsequent
PRECHARGE command. tWT starts at the end of the data
burst, regardless of the data mask condition.
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