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參數(shù)資料
| 型號： | W3E64M72S-266BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 SYNCHRONOUS DRAM, 0.75 ns, PBGA219 |
| 封裝： | 25 X 32 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 674K |
| 代理商： | W3E64M72S-266BI |
W3E64M72S-XBX
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
June 2005
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DENSITY COMPARISONS
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register denition,
command descriptions and device operation.
Discrete Approach
SAVINGS – Area: 66% – I/O Count: 55%
Area = 800mm2
Area: 9 x 265mm2 = 2,385mm2
I/O Count = 219 Balls
I/O Count: 9 x 54 pins = 486 pins
11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
ACTUAL SIZE
25
32
White Electronic Designs
W3E64M72S-XBX
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3E64M72S-266BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-266ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-266ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-266ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-266SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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