參數(shù)資料
型號(hào)： W28J321BB90L
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 2M X 16 FLASH 2.7V PROM, 90 ns, PBGA48
封裝： 8 X 11 MM, 0.75 MM PITCH, TFBGA-48
文件頁數(shù)： 45/47頁
文件大?。?/td> 1385K
代理商： W28J321BB90L
W28J321B/T
Publication Release Date: April 11, 2003
- 7 -
Revision A4
6. PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0
A20
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
A15
A20: Main Block Address.
A12
A20: Boot and Parameter Block Address.
DQ0
DQ15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, status register and identifier code read cycles.
Data pins float to high impedance when the chip is deselected or outputs are
disabled. Data is internally latched during write cycle.
#CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers.
#CE-high deselects the device and reduces power consumption to standby levels.
#RESET
INPUT
RESET: Resets the device internal automation. #RESET-high enables normal
operation. When driven low, #RESET inhibits write operations which provides data
protection during power transitions. Exit from reset mode sets the device to read array
mode. #RESET must be VIL during power-up.
#OE
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
#WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the #WE pulse.
#WP
INPUT
WRITE PROTECT: When #WP is VIL, boot blocks cannot be written or erased. When
#WP is VIH, locked boot blocks can not be written or erased. #WP is not affected
parameter and blocks.
VPP
SUPPLY
BLOCK ERASE, FULL CHIP ERASE, WORD WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words or
configuring lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block
erase, full chip erase, word write and lock-bit configuration with an invalid VPP (see
DC Characteristics) produce spurious results and should not be attempted. Applying
12V
±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles
on each block. VPP may be connected to 12V ±0.3V for a total of 80 hours maximum.
VDD
SUPPLY
DEVICE POWER SUPPLY: Do not float any power pins. With VDD ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VDD voltage
(see DC Characteristics) produce spurious results and should not be attempted.
VSS
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Table 1.
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