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參數(shù)資料
| 型號： | W28J321BB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 11 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 24/47頁 |
| 文件大?。?/td> | 1385K |
| 代理商： | W28J321BB90L |
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W28J321B/T
- 30 -
Bus Operation
Command
Comments
Write
Read Status
Register
Data = 70H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write
Setup OTP
Program
Data = C0H
Addr = X
Write
OTP
Program
Data = Data to Be Written
Addr = Location to Be
Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent OTP programs.
SR full status check can be done after each OTP program,
or after a sequence of OTP programs.
Write FFH after the last OTP program operation to place
device in read array mode.
Start
Write 70H
SR.7=
Write C0H
Read Status
Register
SR.7=
Full Status
Check if Desired
OTP Program
Complete
Read Status
Register
Write Data
and Address
1
0
1
0
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
SR.1=
SR.4=
0
1
Vpp Range Error
Device Protect Error
OTP Program
Sucessfully
OTP Program
Sucessfully
Bus Operation Command
Comments
Standby
Check SR.3
1 =
VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4
1 = Data Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated OTP Program Flowchart
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