參數(shù)資料
型號(hào)： VL6524
廠商： 意法半導(dǎo)體
英文描述： VGA single-chip camera module
中文描述： 顯卡單芯片相機(jī)模塊
文件頁(yè)數(shù)： 60/70頁(yè)
文件大?。?/td> 505K
代理商： VL6524
Electrical characteristics
VL6524/VS6524
60/70
13.4
AC electrical characteristics
13.4.1
External clock
The VL6524/VS6524 requires an external clock. This clock is a CMOS digital input. The
clock input is fail-safe in power down mode.
Table 36.
13.4.2
Chip enable
CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE.
See
Chapter 4
for power down and for power-up sequence.
13.4.3
I2C slave interface
VL6524/VS6524 contains an I2C-type interface using two signals: a bidirectional serial data
line (SDA) and an input-only serial clock line (SCL). See
Chapter 10
for detailed description
of protocol.
Table 37.
External clock
CLK
Range
Unit
Min.
Typ.
Max.
DC coupled square wave
VDD
V
Clock frequency (normal operation)
6.50
6.50, 8.40, 9.60, 9.72, 12.00,
13.00, 16.80, 19.20, 19.44
26
MHz
Serial interface voltage levels
(1)
1.
Maximum V
IH
= V
DDmax
+ 0.5 V
C
b
= capacitance of one bus line in pF
Symbol
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
V
HYS
Hysteresis of Schmitt Trigger
Inputs
V
DD
> 2 V
N/A
N/A
0.05 V
DD
-
V
V
DD
< 2V
N/A
N/A
0.1 V
DD
-
V
LOW level output voltage
(open drain) at 3mA sink current
V
OL1
V
OL3
V
DD
> 2 V
V
DD
< 2V
0
0.4
0
0.4
V
N/A
N/A
0
0.2 V
DD
V
V
OH
HIGH level output voltage
N/A
N/A
0.8 V
DD
V
t
OF
Output fall time from V
IHmin
to
V
ILmax
with a bus capacitance
from 10 pF to 400 pF
-
250
20+0.1C
b(2)
2.
250
ns
t
SP
Pulse width of spikes which must
be suppressed by the input filter
N/A
N/A
0
50
ns
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參數(shù)描述
VL6524Q0MH 制造商:STMicroelectronics 功能描述:VGA SINGLE-CHIP CAMERA MODULE - Trays
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VL6624 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:1.3 Megapixel single-chip camera module
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