參數(shù)資料
型號(hào)： VL6524
廠商： 意法半導(dǎo)體
英文描述： VGA single-chip camera module
中文描述： 顯卡單芯片相機(jī)模塊
文件頁(yè)數(shù)： 31/70頁(yè)
文件大?。?/td> 505K
代理商： VL6524
VL6524/VS6524
Getting started
31/70
9
Getting started
9.1
Initial power up
Before any communication is possible with the VL6524/VS6524 the following steps must
take place:
1.
Apply VDD (1.8V or 2.8V)
2.
Apply AVDD (2.8V)
3.
Apply an external CLOCK (6.5 MHz to 26 MHz)
4.
Assert CE line HIGH
These steps can all take place simultaneously. After these steps are complete a delay of
200 μs is required before any I2C communication can take place, see
Figure 3: Power up
sequence
.
9.2
Minimum startup command sequence
1.
Enable the microprocessor - before any commands can be sent to the
VL6524/VS6524, the internal microprocessor must be enabled by writing the value
0x06 to the MicroEnableregister 0xC003 (
Table 7: Low-level control registers
).
Enable the digital I/O - after power up the digital I/O of the VL6524/VS6524 is in a high-
impedance state (‘tri-state’). The I/O are enabled by writing the value 0x01 to the
Enable I/Oregister 0xC034 (
Table 7: Low-level control registers
).
The user can then program the system clock frequency and setup the required output
format before placing the VL6524/VS6524 in RUN mode by writing 0x02 to the
bUserCommand register 0x0180 (
Table 9: Mode control
).
2.
3.
The above three commands represent the absolute minimum required to get video data
output.
The default configuration results in an output of VGA, 30 fps, YUV data format with ITU
embedded codes requiring a external clock frequency of 12MHz.
In practice the user is likely to require to write some additional setup information prior to
receive the required data output.
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參數(shù)描述
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