參數(shù)資料
型號(hào): VL6524
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁(yè)數(shù): 30/70頁(yè)
文件大小: 505K
代理商: VL6524
Data synchronization methods
VL6524/VS6524
30/70
8.2.2
Vertical synchronization (VSYNC)
The VSYNC signal is controlled by the bVSyncSetup register. The following options are
available:
enable/disable
select polarity
manual or automatic
In automatic mode the VSYNC signal envelops all the active video lines in the output frame
regardless of the programmed image size as shown in
Figure 16
.
Figure 16.
VSYNC timing example
If manual mode is selected then the line number for VSYNC rising edge and falling edge is
programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLineH
bVsyncRisingLineLregisters, the pixel position for VSYNC rising edge is programmed in the
bVsyncRisingPixelHand bVsyncRisingPixelL registers. Similarly the line count for the falling
edge position is specified in the bVsyncFallingLineHand bVsyncFallingLineLregisters, and
the pixel count is specified in the bVsyncFallingPixelHand bVsyncFallingPixelL registers
described in
Table 29: Output formatter control
.
BLANKING
BLANKING
V=1
V=0
V=1
V=0
vsync
ACTIVE
VIDEO
ACTIVE
VIDEO
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