參數(shù)資料
型號： VG36641641DT
廠商： Electronic Theatre Controls, Inc.
英文描述： CMOS Synchronous Dynamic RAM
中文描述： 同步動態(tài)隨機(jī)存儲器的CMOS
文件頁數(shù)： 22/69頁
文件大?。?/td> 1364K
代理商： VG36641641DT
Document :1G5-0177
Rev.2
Page 22
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
9. Read / Writw Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previ-
ous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Write B
WRITE to WRITE Command Interval
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will
begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
READ to READ Command Interval
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VG36641641DT-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM
VG36641641DT-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM
VG36641641DT-7L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM
VG36641641DT-8H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM
VG36641641DTL-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM
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