參數(shù)資料
型號(hào): VG36641641DT
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous Dynamic RAM
中文描述: 同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器的CMOS
文件頁數(shù): 19/69頁
文件大?。?/td> 1364K
代理商: VG36641641DT
Document :1G5-0177
Rev.2
Page 19
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
7.Precharge
The precharge command can be asserted anytime after t
RAS(min.)
is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
idle state after t
RP(min.)
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
In order to write all data to the memory cell correctly, the asynchronous parameter ”t
DPL
” must be satisfied. The
t
DPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of
clocks can be calculated by dividing t
DPL(min.)
with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS latency
2
Read
-1
Write
+ t
DPL(min.)
+ t
DPL(min.)
3
-2
Burst lengh=4
T7
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(t
RAS
is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
Read
T0
T1
T2
T3
T4
T5
T6
PRE
Hi - Z
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