- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359377 > VG36641641DT (Electronic Theatre Controls, Inc.) CMOS Synchronous Dynamic RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | VG36641641DT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Synchronous Dynamic RAM |
| 中文描述： | 同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器的CMOS |
| 文件頁(yè)數(shù)： | 1/69頁(yè) |
| 文件大?。?/td> | 1364K |
| 代理商： | VG36641641DT |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)
Document :1G5-0177
Rev.2
Page 1
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Description
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous
dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
Single 3.3V (
) power supply
High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
Fully synchronous operation referenced to clock rising edge
Possible to assert random column access in every cycle
Quad internal banks controlled by A12 & A13 (Bank Select)
Byte control by LDQM and UDQM for VG36641641D
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
X4, X8, X16 organization
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64ms
Burst termination by Burst stop and Precharge command
0.3V
±
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VG36641641BT | CMOS Synchronous Dynamic RAM |
| VG509A | EPROM-Based 8-bit micro-controller |
| VGFX200K-SERIES | ASIC |
| VGFX20K-SERIES | ASIC |
| VGFX350K-SERIES | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36641641DT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM |
| VG36641641DT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM |
| VG36641641DT-7L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM |
| VG36641641DT-8H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM |
| VG36641641DTL-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous Dynamic RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。