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參數(shù)資料
| 型號： | VG36128161BFL-7H |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封裝： | 10 X 9 MM, VFBGA-54 |
| 文件頁數(shù)： | 7/69頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | VG36128161BFL-7H |
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Document :1G5-0183
Rev.5
Page 15
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
3. Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or
malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode regiser.
After these sequence, the SDRAM is in idle state and ready for normal operation.
4. Programming the Mode Register
The mode register is programmed by the mode register set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
: A13 through A7
CAS latency
: A6 through A4
Wrap type
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data
will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The value can be pro-
grammed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
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PDF描述 |
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| VG36128161BT-7H | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| VG36128161BFL-7L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| VG95234E32-5P1X | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36128161BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
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