參數(shù)資料
型號： VECANA01
英文描述： 10-Channel, 12-Bit DATA ACQUISITION SYSTEM
中文描述： 10通道，12位數(shù)據(jù)采集系統(tǒng)
文件頁數(shù)： 8/17頁
文件大?。?/td> 329K
代理商： VECANA01
VECANA01
SBAS155
8
SH
1
MUX
1
MUX
2
MUX
6
MUX
7
MUX
3
MUX
4
MUX
5
SH
2
SH
6
SH
7
SH
4
SH
5
2.5V
Ref
SH
3
Input Setup
Register
ADC
3
Control
Logic
NPSH
Conv
Sample
IVP/N
B1P/N
B2P/N
2
2
2
IWP/N
AN1P/N
AN2P/N
AN3P/N
2
2
2
2
REFOUT
REFIN
IUP/N
A1P/N
A2P/N
2
2
2
2
2
NPSH
2
2
2
2
2
2
PGA
3
AN1 Through AN3
IW Only
2
2
ADC
2
PGA
2
2
ADC
1
PGA
1
2
2
2
Decoder
DAC
8-Bit
8
2
3
2
ADOUT1
ADOUT2
ADOUT3
ADIN
DAOUT
NPSH
ADCLK
ADCONV
ADBUSY
DATACLK
2
2
2
Input
Select
Gain
Select
Conv
Conv
Conv
DAC
Input
Ref
Ref
Ref
Ref
2
U_COMP
2
U_ILIM
A_1
A_2
V_COMP
B_1
B_2
W_COMP
V_ILIM
W_ILIM
DAIN
2
2
2
2
2
2
FIGURE 1. Functional Diagram.
FUNCTIONAL DESCRIPTION
The VECAN01 is a triple 12-bit SAR A/D converter that
operates from dual
±
5V power supplies. The part contains
three 12-bit successive approximation ADCs, multiplexer
for 10 fully differential inputs, 5 differential input synchro-
nized sample-and-hold amplifiers, plus two asynchronous
sample-and-hold amplifier. It communicates over three syn-
chronous SPI/SSI serial output and one input ports. The
VECANA01 operates on external clock that also determines
the output data rate (see Figure 2).
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