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參數(shù)資料
| 型號(hào)： | VECANA01 |
| 英文描述： | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| 中文描述： | 10通道，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 329K |
| 代理商： | VECANA01 |
VECANA01
SBAS155
14
GAIN
SELECT
0-1
GAIN
SETTING
FULL SCALE
INPUT
0
H
1
H
2
H
3
H
5.0V/V
2.5V/V
1.25V/V
1.0V/V
±
0.5V
±
1.0V
±
2.0V
±
2.5V
TABLE X. Gain Select Information.
DESCRIPTION
GAIN SELECT CODE
0
1
2
3
GAIN
5V/V
2.5V/V
1.25V/V
1.0V/V
FULL SCALE RANGE
±
0.5V
±
1.0V
±
2.0V
±
2.5V
HEX CODE
BINARY CODE
+Full Scale (FS –1LSB)
One Bit above Mid-Scale
Mid-Scale
One Bit Below Mid-Scale
–Full Scale
+0.49976
+0.244mV
0V
–0.244V
–0.500V
+0.9995V
+0.488mV
0V
–0.488mV
–1.000V
+1.999V
+0.976mV
0V
–0.976mV
–2.000V
+2.499
+1.22mV
0V
–1.22mV
–2.500V
7FF
H
001H
000
H
FFF
H
800
H
0111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0000
NOTE: The programmable gain function applies to all three input channels for ADC
and ADC
. However, the programmable gain function only applies to the
first input (IW) for ADC
3
. The other three inputs (AN1, AN2, and AN3) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus
have a fixed
±
2.5V full scale input range.
ANALOG INPUT
BINARY TWO’S COMPLIMENT FORMAT
TABLE IX. Analog Input - Digital Output Relationships.
DIGITAL OUTPUT
Input Select = 1H—
Input AN3 is converted by ADC
3
. The
output of the asynchronous sample holds, SH
6
and SH
7
, are
converted by PGA
1
/ADC
1
and PGA
2
/ADC
2
, respectively.
Note that the inputs to SH
6
and SH
7
are determined by
previous Input Select values (see Table VIII). Thus, to
properly convert the output of one of the asynchronous
sample holds it is first necessary to choose its input with a
previous conversion cycle. Also, the output of SH
6
or SH
7
will only be converted if NPSH goes low before the
ADCONV command is received.
Input Select = 0 H—
AN3 is converted by ADC
3
. The
inputs to PGA
1
/ADC
1
and PGA
2
/ADC
2
are undefined.
PGA GAIN
The PGA gain is determined by the Gain Select portion (bits
8 and 9) in the ADIN word (see Figure 2). There is one gain
input that sets the same gain for all three PGAs. The gain
values and allowable full-scale inputs are shown in Table X.
For channels one and two the PGAs set the gain for all three
analog inputs. For the third channel, only the IW input is
gain changed by the PGA. Inputs AN1, AN2, and AN3 are
connected to A/D converter three at a fixed gain of 1.0V/V
regardless of the Gain Select value.
CONVERSIONS FROM THE
ASYNCHRONOUS SAMPLE HOLDS
Decoding the Input Select value also determines which
inputs are applied to the two asynchronously controlled
sample holds (SH
6
and SH
7
) (see Table VIII.) One of the
three possible inputs is selected by the Input Select value
being 4, 5, or 6. The “No Effect” states indicate that these
values of Input Select have no effect on the multiplexers at
the input of SH
6
and SH
7
. When one of the “No Effect”
values of Input Select is presented, the multiplexers will not
be changed (i.e., their condition is determined by the last 4,
5, or 6 value of Input Select that existed prior to the “No
Effect” state). Note that Input Select = 1
H
presents the output
of SH
6
and SH
7
to PGA
1
/ADC
l
and PGA
2
/ADC
2
, respec-
tively (see Table VII). Therefore, in order to properly con-
vert the asynchronous sampled signals, it is first necessary to
choose an input signal (Input Select equal 5 or 6 in Table
VIII) with one load/convert cycle and then convert the
sample hold output (Input Select = 4 in Table VII) in a
following conversion cycle.
POWER SUPPLY
The VECANA01 requires an analog and digital supply
voltage of
±
5V. The substrate is connected to UP5V. The
voltage difference between the analog and digital supply pin
is not allowed to exceed a maximal value of 300mV. For this
reason the circuit shown in Figure 7 is recommended for the
power supply. The analog and digital power supplies are
driven by a common source. Intermediate resistors provide
for decoupling. Local current-limited voltage regulators gen-
erate the
±
5V from the analog supply voltages
±
U
B
. This
guarantees a further noise reduction. The diodes are respon-
sible for protecting the regulation and prevent polarity inver-
sion. The zener diode protects against over-voltage possible
from over-voltages to the analog inputs. Typical values for
the resistors and capacitors are:
R
A
≈
3
R
D
≈
3
C
D
≈
22
μ
F
C
A
≈
22
μ
F
C
B
≈
100nF
C
R
≈
2.2
μ
F
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