參數(shù)資料
型號(hào)： VECANA01
英文描述： 10-Channel, 12-Bit DATA ACQUISITION SYSTEM
中文描述： 10通道，12位數(shù)據(jù)采集系統(tǒng)
文件頁(yè)數(shù)： 1/17頁(yè)
文件大小： 329K
代理商： VECANA01
VECANA01
10-Channel, 12-Bit
DATA ACQUISITION SYSTEM
FEATURES
G
10 FULLY DIFFERENTIAL INPUTS
G
5 SIMULTANEOUS SAMPLED CHANNELS
PLUS 2 SYNCHRONIZED SAMPLING
CHANNELS
G
3 SYNCHRONIZED 12-BIT ADCs
G
12.8
μ
s THROUGHPUT RATE
G
DIGITALLY SELECTABLE INPUT RANGES
G
±
5V POWER SUPPLIES
G
SERIAL DIGITAL INPUT/OUTPUTS
G
7 SIGN AND 3 DIGITALLY
PROGRAMMABLE WINDOW COMPARATOR
APPLICATIONS
G
AC MOTOR SPEED CONTROLS
G
THREE PHASE POWER CONTROL
G
UNINTERRUPTABLE POWER SUPPLIES
G
VIBRATION ANALYSIS
DESCRIPTION
The VECANA01 consists of three 12-bit analog-to-
digital converters preceded by five simultaneously
operating sample-hold amplifiers, and multiplexers
for 10 differential inputs. The ADCs have simulta-
neous serial outputs for high speed data transfer and
data processing.
The VECANA01 also offers a programmable gain am-
plifier with programmable gains of 1.0V/V, 1.25V/V,
2.5V/V, and 5.0V/V. Channel selection and gain selec-
tion are selectable through the serial input control word.
The high through put rate is maintained by simulta-
neously clocking in the 13-bit input control word for the
next conversion while the present conversions are
clocked out.
The part also contains an 8-bit digital-to-analog con-
verter whose digital input is supplied as part of the
input control word.
Copyright 2000, Texas Instruments Incorporated
SBAS155
Printed in U.S.A. October, 2000
VECANA01
ADC
2
12-Bit
PGA
2
SH
2
MUX
2
ADOUT2
B1P/N
2
2
2
IVP/N
B2P/N
ADC
3
12-Bit
PGA
3
SH
3
MUX
3
ADOUT3
AN1P/N
2
2
2
IWP/N
AN3P/N
ADC
1
12-Bit
PGA
1
SH
1
MUX
1
ADOUT1
A1P/N
2
2
2
IUP/N
A2P/N
AN2P/N
2
Logic
Ref
IRegister
8-Bit
DAOUT
ADBUSY
COMP
3
ILIM
DAIN
ADIN
ADCONV
ADCLK
REFOUT
DAC
Input Select
Gain Select
7
7
www.ti.com
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