- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359354 > VECANA01 10-Channel, 12-Bit DATA ACQUISITION SYSTEM PDF資料下載
參數(shù)資料
| 型號(hào)： | VECANA01 |
| 英文描述： | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| 中文描述： | 10通道，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 329K |
| 代理商： | VECANA01 |
VECANA01
SBAS155
10
VOLTAGE REFERENCE
The VECANA01 contains an internal 2.5V voltage refer-
ence. It is available externally through an output buffer
amplifier. If it is desired to use an external reference, one
may be connected at the REFIN pin. The output resistance
of this pin for the external reference voltage is typically
7k
. This then overrides the internal 2.5V reference and is
connected to the A/D converter. It is also available as a
buffered output at the REFOUT pin.
The reference voltage shall be buffered by an external
capacitor (approx. 2.2
μ
F) on the REFIN pin and also on the
REFOUT pin (see Figure 3), as close as possible to the pin.
DIGITAL-TO-ANALOG CONVERTER
An 8-bit DAC provides 256 output voltage levels from 0V
to 2.499V (see Table I for input/output relationships). The
DAC is controlled by the DAC Input portion of the input
setup word. The DAC Input portion of the word is strobed
into the DAC at the end of the conversion cycle (14th CLK
pulse in Figure 2).
DIGITAL INPUT
DAC INPUT
0-7
ANALOG OUTPUT
HEX
CODE
BINARY
CODE
00
H
01
H
FF
H
0000 0000
0000 0001
1111 1111
0V
+0.0098V
+2.499
TABLE I. DAC Input/Output Relationships.
input. This allows the conversion to be synchronous with
system timing so that transient noise effects can be mini-
mized. The ADCLK signal may run continuously or may be
supplied only during convert sequences. The ADBUSY and
DATACLK signals are internally generated and are supplied
to make interfaces with microprocessors easier (see Figures
2 and 9).
POWER-UP INITIALIZATION
When power is applied to the VECANA01, two conversion
cycles are required for initialization before valid digital data
is transmitted on the third cycle. The first conversion, after
power is applied, is performed with indeterminate configu-
ration values in the double buffer output of the Input Setup
Register. The second conversion cycle loads the desired
values into the register. The third conversion uses those
values to perform proper conversions and output valid digi-
tal data from each of the A/D converters.
CONFIGURABLE PARAMETERS
Configurable parameters are:
PGA Gain
Input Multiplexer and Sample-and-Hold Selection
DAC Output Voltage
Configuration information for these parameters is contained
in the ADIN word (see Figure 2). As one conversion is
taking place, the configuration for the next conversion is
being loaded into the buffered Input Setup Register via the
ADIN word. Tables I, VII, VIII and X shows information
regarding these parameters.
ANALOG-TO-DIGITAL
CONVERTERS
ARCHITECTURE
The A/D converters are 12-bit, successive approximation
types implemented with a switched capacitor circuitry.
CLOCK RATE
The clock for the A/D converter conversion is supplied
externally at the ADCLK pin. Typical clock frequency for
specified accuracy is 1.25MHz. This results in a complete
conversion cycle (S/H acquisition and A/D conversion) of
10.4
μ
s.
CLOCK
POSITIONS
(1)
DESCRIPTION
FUNCTIONS
2-9
DAC Input
0-7
Gain Select
0-1
Input Select
0-2
Conditions
Sets DAC Output Voltage
10-11
Sets PGA Gains
12-14
Determines Multiplexers
NOTE: (1) See Figure 2, “Clock Pulse Reference No.”
TABLE II. Description of Configurable Parameters.
FIGURE 3. Reference Voltage Connection.
+
REFOUT
7k
2.2
μ
F
2.2
μ
F
Internal
Connection
2.5V
Reference
+
REFIN
REFGND
DAC OUTPUT VOLTAGE
The value of the DAC output voltage is determined by the
DAC Input portion of the ADIN word (bits 0 through 7, see
Figure 2). The 8-bit DAC has 256 possible output steps from
0V to +2.499V. The value of 1LSB is 0.0098V.
OTHER DIGITAL INPUTS AND OUTPUTS
Sampling and conversion is controlled by the ADCONV and
ADCLK input (see Figure 2). The VECANA01 is designed
to operate from an external clock supplied at the ADCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VEF44A | PLASTIC QUAD FLATPACK 10 X 10 MM 44 LEAD |
| VEN2AAA | TWEEZERS ROUND POINT |
| VESD05A1-02V | Single-line ESD protection diode |
| VESD05A8-HN2 | 8-Lines ESD protection diode array |
| VESD05C-FC1 | Bidirectional ESD protection diodes in flip-chip 1005 size; |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VECANA01G3 | 功能描述:數(shù)據(jù)轉(zhuǎn)換系統(tǒng) 10 Ch 12B Data Acquisition System RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| VECR22M1HTR-0405 | 功能描述:鋁質(zhì)電解電容器-SMD 50 volts .22uF 20% 4x5.3 RoHS:否 制造商:Vishay/BC Components 電容:2200 uF 容差:20 % 電壓額定值:16 V ESR: 工作溫度范圍:- 55 C to + 150 C 尺寸:16 mm W x 16 mm L x 21 mm H 產(chǎn)品:High Temp Electrolytic Capacitors |
| VECR33M1HTR-0405 | 功能描述:鋁質(zhì)電解電容器-SMD 50 volts .33uF 20% 4x5.3 RoHS:否 制造商:Vishay/BC Components 電容:2200 uF 容差:20 % 電壓額定值:16 V ESR: 工作溫度范圍:- 55 C to + 150 C 尺寸:16 mm W x 16 mm L x 21 mm H 產(chǎn)品:High Temp Electrolytic Capacitors |
| VECR47M1HTR-0405 | 功能描述:鋁質(zhì)電解電容器-SMD 50 volts .47uF 20% 4x5.3 RoHS:否 制造商:Vishay/BC Components 電容:2200 uF 容差:20 % 電壓額定值:16 V ESR: 工作溫度范圍:- 55 C to + 150 C 尺寸:16 mm W x 16 mm L x 21 mm H 產(chǎn)品:High Temp Electrolytic Capacitors |
| VECS0111 | 制造商:Panasonic Industrial Company 功能描述:CABLE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。