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| 型號： | VECANA01 |
| 英文描述： | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| 中文描述： | 10通道，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 329K |
| 代理商： | VECANA01 |
VECANA01
SBAS155
12
DAC INPUT
U
PLIM
U
NLIM
0H
0V
0V
1H
+0.0098V
–0.0098V
2H
+0.0195V
–0.0195V
0FEH
+2.4805V
–2.4805V
0FFH
+2.4902V
–2.4902V
TABLE V. Over-Current Limit as a Function DAC Input.
IUP – IUN
IVP – IVN
IWP – IWN
U_ILIM
V_ILIM
W_ILIM
(IXP - IXN) > U
PLIM
U
PLIM
> (IXP - IXN) > U
NLIM
U
NLIM
> (IXP - IXN)
0
1
0
TABLE VI. The Limiting Value as Function of DAC Input.
DAIN. See Figure 5 for graphical view of the over limit set
function (typically used for setting the current protection
value), The DAIN value will determine the fixed range.
Normally this pin is connected to DAOUT (the DAC output).
In order to be able to program the range value through the
control value DAC Input word, the DAC Input is an 8-bit wide
unsigned value (controls the digital-to-analog converter output
voltage (DAOUT)). This D/A converter has an output voltage
range of 0V to 2.5V (see Table I).
If the input voltage exceeds the positive range limit (IXP –
IXN > U
PLIM
) or it remains under the negative range (IXP –
IXN < U
NLIM
), then the corresponding window comparator
output is Low (logic “0”) (U_ILIM, V_ILIM, or W_ILIM). If
the input value is within the limits, the comparator output is
High (logic “1”). The input signal and output X_ILIM signals
are shown in Table VI.
The input voltage range of the comparators is the same as the
A/D converter when the Gain Select is 3. The typical value
of the hysteresis of the comparators is 50mV. Figure 5
shows the Logic State of the U_COMP and U_ILIM outputs
for the input signal IVP – IUN. The output resistance of the
D/A converter is approximately 10k
. The output voltage,
DAOUT should be buffered by a capacitor of approximately
100nF (see Figure 6) The resulting time constant is approxi-
mately 1ms and typical does not disturb most applications.
INPUT SIGNALS FOR PGAS/ADCS
Table VII shows the relationships between the value of Input
Select
0-2
and the signals that are converted.
Input Select = 7H—
Synchronously sample and convert
input signals IU, IV, and IW.
IUP - IUN
U
PLIM
= Hysteresis
U
NLIM
U_COMP
U_ILIM
FIGURE 5. Acquisition of the Current Sign and of the Over-
Current.
INPUT SELECT
0-2
HEX
CODE
ANALOG SIGNAL CONNECTED TO
PGA
X
/ADC
X
PGA
1
/ADC
1
PGA
2
/ADC
2
Undefined
Undefined
A_X
via SH
6(1)
B_X
via SH
7(1)
A_2
via SH
1
B_2
via SH
3
A_2 via SH
2
B_2 via SH
4
A1
A1
A1
IU
PGA
3
/ADC
2
AN3
AN3
AN2
AN2
AN1
AN1
AN1
IW
0
H
1
H
2
H
3
H
4
H
5
H
6
H
7
H
000
001
010
011
100
101
110
111
B1
B1
B1
IV
NOTE: (1) See Table VIII for Operation.
BINARY
CODE
TABLE VII. Input Controls for Synchronous Sample Holds.
INPUT SELECT
0-2
HEX
CODE
ANALOG SIGNAL CONNECTED TO
SH
6
SH
7
0
H
1
H
2
H
3
H
4
H
5
H
6
H
7
H
000
001
010
011
100
101
110
111
No Effect
No Effect
No Effect
No Effect
Open
A1
A2
No Effect
No Effect
No Effect
No Effect
No Effect
Open
B1
B2
No Effect
BINARY
CODE
TABLE VIII. Input Controls for Asynchronous Sample
Holds.
Input Select = 4H, 5H, 6H—
Synchronously sample and
convert input signals A1, B1, and AN1. These codes also
cause SH
2
and SH
4
to sample their inputs. Values 4
H
, 5
H
, 6
H
have different effects on the inputs to SH
6
and SH
7
(see
Table VIII).
Input Select = 3H—
Convert A2 via SH
2
, B2 via SH
4
, and
AN2 (A2 and B2 are from the value sampled in a preceding
conversion cycle with Input Select = 4
H
, 5
H
or 6
H
).
Input Select = 2H —
Convert A2 via SH
1
, B2 via SH
3
, and
AN2.
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